1. Technical Field
The present disclosure relates to a bipolar junction transistor and a method for fabricating the same; and more particularly, to a bipolar junction transistor that is compatible with a complementary metal-oxide semiconductor process and a method for fabricating the same.
2. Discussion of the Related Art
In complementary metal-oxide semiconductor (CMOS) technology, an n-type channel metal-oxide-semiconductor field effect transistor (MOSFET) and a p-type channel MOSFET are fabricated in proximity on the same chip. The CMOS technology has been used in various circuit application fields such as high-frequency circuits and high-frequency system-on-chip. The n-channel MOSFET and the p-channel MOSFET are referred to as an NMOS transistor and a PMOS transistor, respectively.
The CMOS devices do not provide a low noise characteristic required for devices configured for high-frequency circuits. The devices configured for high-frequency circuits include, for example, a low noise amplifier (LNA) and a voltage control oscillator (VCO). A bipolar junction transistor having a frequency response characteristic and current driving capability is fabricated on the same chip as the CMOS device. The high performance bipolar junction transistor is used for a high-frequency circuit, while the CMOS device is used for a logic circuit.
The bipolar junction transistor includes three terminals, that is, a base, an emitter and a collector. For the bipolar junction transistor fabrication, several mask processes and ion implantation processes are performed to form the three terminals with different depths in a substrate. Various methods have been used to incorporate a bipolar junction transistor with a standard CMOS process while maintaining characteristics of the bipolar junction transistor. Processes that fabricate the bipolar junction transistor and the CMOS device simultaneously have been developed.
According to one process, an ion implantation process for forming an n-well in which a PMOS transistor will be formed is performed to form a collector region. Ion implantation of arsenic (As) for forming lightly doped drain (LDD) regions of an NMOS transistor forms an emitter region and a collector buffer. A base region is formed through ion implantation of boron for forming LDD regions of the PMOS transistor. An emitter contact and a collector contact are formed by implanting a highly doped n+-type impurity for forming a source region and a drain region of the NMOS transistor. A base contact is formed through ion implantation of a highly doped p+-type impurity for forming a source region and a drain region of the PMOS transistor.
However, since the LDD ion implantation and a high doping level of the n-well ion implantation are applied to form the base region and the collector region, respectively, a large scale of the base width modulation occurs and the early voltage decreases. During the base width modulation, a depletion region between the base region and the collector region increases while the base width decreases. This large scale of the base width modulation impairs stability of the bipolar junction transistor. It is difficult to form the stable base region because of an extremely low doping level in the base region. In addition, the doping level in the base region, the width thereof and the doping level in the collector region are fixed to the CMOS process. Thus, the operation characteristics of the bipolar junction transistor and the CMOS device may not be satisfied simultaneously.
In another process, using a relatively deep n-well instead of using a well for a MOS transistor to improve a high-frequency operation characteristic and to reduce an incidence of noise coupling from a logic circuit to a high-frequency circuit has been suggested. According to this process, the deep n-well having a low doping level is to employed as a collector region, and an ion implantation process for forming a p-well in which an NMOS transistor will be formed is performed to form a base region. Another ion implantation process for forming an n-well region in which a PMOS transistor will be formed is performed to form a collector buffer. Ion implantation of a highly doped n+-type impurity for forming source/drain regions of the NMOS transistor forms an emitter region and a collector contact. A base contact is formed by ion-implanting a highly doped p+-type impurity for forming source/drain regions of the PMOS transistor.
However, since the base region is formed through the ion implantation process for forming the p-well region in which the NMOS transistor will be formed, the base width depends on the p-well process of the NMOS transistor. Therefore, the base region and the p-well have the same depth. The depth of the p-well for the NMOS transistor is far larger than the width of the base region required by the high-performance bipolar junction transistor. Herein, the width of the base region is a measurement of the effective base region in the perpendicular direction from an upper surface of a substrate. That is, the base width is substantially large. Hence, there exists a difficulty in satisfying the high-quality operation characteristic suitable for the high-frequency circuit as the transition time of carriers in the base region increases.
Another known method reduces a base width of a CMOS device through counter-doping. According to this method, an ion implantation process for forming a deep n-well is applied to form a collector region, and another ion implantation process for forming a p-well in which an NMOS transistor will be formed is used to define a boundary beneath the base region. The counter-doping is executed to a p-well region by performing an ion implantation process for forming an n-well in which a PMOS transistor will be formed for defining a boundary above the base region and an emitter region. The p-well is formed deeper than the n-well, and a base width is determined by a depth difference between these two wells.
In the CMOS process, the n-well and the p-well generally have substantially the same depth. Thus, it is difficult to adjust the base width through the n-type counter-doping. The emitter region subjected to the counter-doping has a high level of resistivity, thereby degrading performance of the bipolar junction transistor at a high-frequency region. Also, a gain value is low since a doping level of the emitter region is low.
Therefore, a need exists for a method for forming a bipolar junction transistor with high gain and high-performance while being compatible with the CMOS process.